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Description

 

The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.

Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\₁ and OE₀) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A₀, A₁, A₂ inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state.

Features

• Select One of Eight Data Outputs
  • Active Low for CD74HC137 and CD74HCT137
  • Active High for ’HC237 and CD74HCT237
• I/O Port or Memory Selector
• Two Enable Inputs to Simplify Cascading
• Typical Propagation Delay of 13ns at V_CC = 5V, 15pF, T_A = 25°C (CD74HC237)
• Fanout (Over Temperature Range)
  • Standard Outputs. . . . 10 LSTTL Loads
  • Bus Driver Outputs. . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . –55°C to 125°C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
  • 2V to 6V Operation
  • High Noise Immunity: N_IL = 30%, N_IH = 30%, of V_CC at V_CC = 5V
• HCT Types
  • 4.5V to 5.5V Operation
  • Direct LSTTL Input Logic Compatibility, V_IL = 0.8V (Max), V_IH = 2V (Min)
  • CMOS Input Compatibility, I_l 1µA at V_OL, V_OH

Data sheet acquired from Harris Semiconductor