0 είδη στο καλάθι,   συνολική αξία: 0,00 €

CD4029B consists of a four-stage binary or BCD-decade up/down counter with provisions for look-ahead carry in both counting modes. The inputs consist of a single CLOCK, CARRY-IN\ (CLOCK ENABLE\), BINARY/DECADE, UP/DOWN, PRESET ENABLE, and four individual JAN signals, Q1, Q2, Q3, Q4 and a CARRY OUT\ signal are provided as outputs.

A high PRESET ENABLE signal allows information on the JAM INPUTS to preset the counter to any state asynchronously with the clock. A low on each JAM line, when the PRESET-ENABLE signal is high, resets the counter to its zero count. The counter is advanced one count at the positive transition of the clock when the CARRY-IN\ and PRESET ENALBE signals are low. Advancement is inhibited when the CARRY-IN\ or PRESET ENABLE signals are high.

_Features

• _{Medium-speed operation… 8 MHz (typ.) @ CL = 50 pF and VDD–VSS = 10 V}
• _{Multi-package parallel clocking for synchronous high speed output response or ripple clocking for slow clock input rise and fall times}
• _{"Preset Enable" and individual "Jam" inputs provided}
• _{Binary or decade up/down counting}
• _{BCD outputs in decade mode}
• _{100% tested for quiescent current at 20 V}
• _{5-V, 10-V, and 15-V parametric ratings}
• _{Standardized, symmetrical output characteristics}
• _{Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C}
• _{Noise margin (full package-temperature range) =
  1 V at VDD = 5 V
  2 V at VDD = 10 V
  2.5 V at VDD = 15 V}
• _{Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"}
• _{Applications:}
  • _{Programmable binary and decade counting/frequency synthesizers-BCD output}
  • _{Analog to digital and digital to analog conversion}
  • _{Up/Down binary counting}
  • _{Magnitude and sign generation}
  • _{Up/Down decade counting}
  • _{Difference counting}