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Dual J-K Flip Flop

The 4027B dual J-K flip-flop has independent J, K, Clock (C), Set (S) and Reset (R) inputs for each flip-flop. These devices may be used in control, register, or toggle functions.

Features
Diode Protection on All Inputs
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Swing Independent of Fanout
Logic Edge-Clocked Flip-Flop Design: Logic state is retained indefinitely with clock level either high or low;information is transferred to the output only on the positive-going edgeof the clock pulse
Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range
Pin-for-Pin Replacement for CD4027B